The present invention related to a high inductance and high-Q inductor fabricated by multilevel interconnect technology, and, more in particular, to a spiral inductor having more than 3 spiral coil patterns with the connection code of edge end terminal to edge and central end terminal end to center to generate the same current flow path in all spiral coils.
Active devices such as CMOS and Bipolar transistors have been successfully implemented in integrated circuits (IC) by using current monolithic technology. Passive devices such as resistors and capacitors can be fabricated in current IC technology. Many commercial products operating at radio frequency (RF) band grow faster and become more popular in wireless communication market. Gradually, system-on-chip (SOC) concept would be used in the future integrated circuit (IC) technology. Therefore, excellent inductor design and process need more elaborate development work to achieve SOC RF IC circuits.
U.S. Pat. No. 5,446,311 describes a conventional spiral inductor fabricated with current IC interconnect technology, shown in FIG. 1A. In order to reduce series resistance of metal lines, this inductor structure uses several layers of metal connected with nearby level of metal through multiple via plug arrays. As shown in FIG. 1A, the first metal level 1 is used to as a cross-under to make connection to one end terminal 5 of the spiral metal layer 2. The spiral coils of neighboring metal layers are shunted and connected through via plugs in parallel way. The disadvantage of the prior art is to have quite large inductor area with large parasitic capacitance.
U.S. Pat. No. 5,656,849 improves the inductance of a conventional inductor by using upper spiral coils and lower spiral coils with the same current direction. The advantage of this prior art is to generate more magnetic flux from the summation of lower spiral coil and upper spiral coil contributions. Therefore, the inductance increases as magnetic flux increases. However, the disadvantage of this prior art uses only two metal levels to fabricate the inductor. The inductor with higher inductance needs more spiral coil turns in layout design. Only two metal level can not improve quality factor because of very large inductor layout area. The present invention can increase quality factor by using more metal levels to increase inductance and simultaneously has small inductor layout area. For example, RF IC circuit needs some 18-turn inductors with large inductance and good quality factor. The prior art of U.S. Pat. No. 5,446,311 designs very large inductor layout area with 18-turn spiral coil. According to the prior art of U.S. Pat. No. 5,656,849, this inductor has 9-turn spiral coil for each metal level with large inductor layout. The present invention would design the inductor with 3-turn spiral coil in each metal level to significantly reduce inductor layout area.
The present invention is related to a high inductance and high-Q inductor structure which improve disadvantages of the prior arts. The invention uses multilevel interconnect technology to fabricate a high inductance and high-Q inductor which comprises at least three spiral coil patterns with the same current flow direction. The edge terminal of the first spiral coils is connected with the edge terminal of the second spiral coils and the central terminal of the second spiral coil is connected with the central terminal of the third spiral coils through via plugs. Because of reflection and rotation transformations in the invention, total inductor layout area is much smaller than prior arts with the same inductance.